1. Field of the Invention
The present invention relates to a delay circuit utilizing the Miller effect of a capacitance, suitable for integrated circuits and circuits mounted on a printed circuit board.
2. Description of the Prior Art
There have been proposed various delay circuits for delaying signal transmission to adjust the timing of operation in integrated circuits and circuits mounted on a printed circuit board.
Shown in FIG. 11 is a conventional delay circuit. This delay circuit has an input terminal 1 to which a signal Si is applied, and two output terminals 2 and 3 at which signals So1 and So2 appear, respectively. Signal transmission lines 4 and 5 are connected to the input terminal 1. A delay circuit 6 comprising two inverters connected in series is provided in the line 5. An inverter 7 for signal inversion is connected to the line 4. An inverter 8 for signal inversion is connected to the output of the delay circuit 6. The respective outputs of the inverters 7 and 8 are connected to a NAND gate 9, and the output of the NAND gate is connected to the output terminal 2. The line 4 and the output of the delay circuit 6 are connected to an AND gate 10, and the output of the AND gate 10 is connected to the output terminal 3. In FIG. 12, S1 is a signal carried by the line 4, and S2 is a signal which appears at the output of the delay circuit 6.
FIG. 12 is a waveform chart showing the signals transferred through and appearing at the output terminals of the delay circuit of FIG. 11. The clock signal Si is applied to the input terminal 1 to obtain the two clock signals Sol and So2 which are not overlapping each other. The clock signal Si is delayed slightly by the capacitance of the line 4 to ground and is transmitted in the signal S1 through the line 4 to the inverter 7 and the AND gate 10. The clock signal Si is delayed by a predetermined time by the capacitance of the line 5 to ground and is transmitted in the signal S2 through the line 5 to the inverter 8 and the AND gate 10. The top logical product So2 of the signals S1 and S2 appears at the output terminal 3. The signals S1 and S2 are applied to the inputs of the NAND gate 9 after being inverted respectively by the inverters 7 and 8, and then the signal So1 appears at the output terminal 2. Thus, the two clock signals So1 and So2 having a predetermined phase difference therebetween are obtained.
Referring to FIG. 13 showing another conventional delay circuit, the delay circuit has an input terminal 20 to which a signal Si is applied, and an output terminal 21 at which an output signal So appears. Signal transmission lines 22 and 23 are connected to the input terminal 20. A delay circuit 24 comprising an even number of inverters is provided in the line 23. The line 22 is connected through a switch 25 which is controlled by a control signal Sa to the output terminal 21. The output of the delay circuit 24 is connected through a switch 26 which is controlled by an inversion control signal Sb to the output terminal 21. In using the line 22, the switch 25 is closed by the control signal Sa and is opened the switch 26 by the inversion control signal Sb. Then, the signal Si applied to the input terminal 20 is transmitted in the signal So through the switch 25 after being delayed by a time Tpd1 by the capacitance of the line 22 to ground and appears at the output terminal 21. In using the other line 23 to delay the signal Si more than a ordinary delay, the switch 25 is opened by the control signal Sa and the switch 26 is closed by the inversion control signal Sb. Then, the signal Si applied to the input terminal 20 is transmitted in the signal So through the switch 26 and appears at the output terminal 21 after being delayed by a time Tpd2 by the capacitance of the line 23 to ground and the delay circuit 24. Thus, the signal So delayed by the delay time Tpd1 or Tpd2 is obtained at the output terminal 21 by properly controlling the switches 25 and 26.
The conventional delay circuits 6 and 24, however, have the following problems.
The delay circuit 6 shown in FIG. 11 needs inverters, which increases the number of component devices and requires an increased size in area. Furthermore, the capacitance of the line 4 to ground delays signals and, when the lines 4 and 5 are disposed adjacently, a coupling capacitance between the lines 4 and 5 delays signals carried by the lines 4 and 5. Accordingly, it is possible that the two clock signals So1 and So2 having an accurate desired time interval therebetween cannot be obtained and the delay time of the delay circuit 6 is obliged to be redesigned.
The delay circuit 24 of FIG. 13, similarly to the delay circuit 6 of FIG. 11, increases the number of component devices and requires an increased size in area. Furthermore, the coupling capacitance between the lines 22 and 23 causes the delay time Tpd1 attributable to the capacitance of the line 22 to ground and the delay time Tpd2 attributable to the earth capacitance of the line 23 to ground to be delayed further by a time corresponding to the coupling capacitance, and hence it is difficult to determine an accurate delay time.